This invention relates to programmable logic devices (PLDs) and, more particularly, to improved bit line sense amplifiers for PLDs.
PLDs and sense amplifiers for use in PLDs are well known as shown, for example, by such references as Hartmann et al. U.S. Pat. No. 4,617,479, Wong et al. U.S. Pat. No. 4,871,930, and Ou et al. U.S. Pat. No. 4,899,070, all of which are hereby incorporated by reference herein.
There is continuing demand for PLDs which have more interconnected devices, are faster, and consume less power than those previously available. However, these are conflicting objectives because as the number of interconnected devices increases, power consumption increases and speed decreases.
Conventional PLD sense amplifiers consume dc (or quiescent) power under certain circumstances which are common in practice. This power consumption can be controlled by adjusting the geometry of output transistors in the PLD sense amplifier; however, doing so affects the output voltage transition rates. With high power consumption, the output transition rates can be rapid, and the low-to-high transition rate can be made substantially equal to the high-to-low transition rate. Reducing the power consumption slows down the low-to-high transition rate. Thus, a compromise between power consumption and low-to-high transition rate must be accepted.
Sense amplifiers configured with complementary bit lines, as sometimes used in electrically programmable read only memory (EPROM) designs, do not consume quiescent power. However, there is an inherent difference in the input to output delay depending on whether the output is switching low to high or high to low. There are two reasons for this effect. Firstly, the circuitry which pulls the output voltage low controls the state of the amplifier and, during an output voltage transition, works against the circuitry which pulls the output voltage high. Thus, the pull-up circuitry must be weaker than the pull-down circuitry. This results in the low-to-high transition being slower than the high-to-low transition. Secondly, the output is pulled low directly by a bit line going low. However, additional circuitry is required to pull the output high when the bit line complement goes low. This additional circuitry introduces extra delay. Thus, the time between a change of state of a bit line and the initiation of a corresponding high-to-low transition of the output is shorter than the time between a change of state of a bit line and the initiation of a corresponding low-to-high transition of the output.
In view of the foregoing, it is an object of this invention to provide a sense amplifier with an increased low-to-high output voltage transition rate and reduced quiescent power consumption when operating with single-ended bit lines.
It is a further object of this invention to provide a sense amplifier with an increased low-to-high output voltage transition rate but which still consumes no quiescent power when operating with complementary bit lines.